The present invention relates generally to the field of digital electronics and circuitry. More particularly, it relates to a circuit for providing clock signals with variable frequency and phase and for transmitting those signals so that they exhibit a low amount of skew relative to data signals and other clock signals.
Digital electronic systems generally include a number of component devices such as processors, bus drivers, memory devices, controllers and programmable logic devices (PLDs). These devices are generally implemented in integrated circuit chips or modules. Clock signals are used throughout an electronic system, such as a computer system, to synchronize communication between the devices as well as within the devices themselves. At the system level, a master clock generator provides a primary reference clock signal at a predetermined operating frequency, which is typically a relatively high frequency.
At both the system and device levels, clock signals of different frequencies are often needed to meet the I/O requirements of different devices (or distinct parts of a device). Clock dividers are therefore commonly used to frequency divide the reference clock signal into one or more clock signals operating at a lower frequency. The frequency division factor is typically an integer such as 2, 3, 4, etc. The frequency-divided clock signals are provided to different devices throughout the system, and, within each device, a phase locked loop (PLL) circuit is typically used to generate an internal clock signal that is synchronized to the external clock signal. In addition, different phases of a clock signal may be used for sequencing logic in devices, especially memory devices such as synchronous dynamic random access memory (SDRAM). In particular, there are generally three types of clocking protocols: clocking on the rising edge of the clock signal, clocking on the falling edge of the clock signal, and clocking on both edges of the clock signal. Depending on the protocol and/or other clocking requirements, the phase of a clock signal may need to be set so that the rising and/or falling edges of the clock signal are appropriately aligned with respect to data transitions.
Within a system or device, the various clock signals are typically generated by clock generating frequency synthesizers and then transmitted, along with data, by drivers or other suitable transmission circuitry. An important requirement in designing a multiple clock system is to avoid or minimize clock skew. Clock skew is the phase difference between two clock signals transmitted to different devices within a system. These phase offsets occur primarily as a result of non-uniform propagation delays in the overall circuitry. When clock skew causes a significant difference in time between the arrival of a clock signal at devices that are interfacing with one another, this may lead to errors and undesirable conditions such as bus contention. As clock frequencies increase, the skew tolerance, i.e., the allowable error margin to account for skew, decreases. Furthermore, skew in the desired alignment between transmitted data and a clock signal must also be minimized, since discrepancies in that alignment can lead to errors and/or a loss of data. Consequently, there is a need for an improved programmable circuit capable of generating clock signals of varying frequency and phase and of transmitting those clock signals, together with data signals, with a very low amount of skew.
The present invention relates to a digital, in one embodiment programmable, circuit for providing one or more clock signals with variable frequency and/or phase, and in which the clock signals exhibit a low amount of skew relative to data signals and other clock signals provided by the circuit. The clock signals may be frequency divided with respect to an input reference clock, and the phase of such clock signals may also be varied to provide a desired alignment with data signals. Since the input clock-to output delays are matched in all possible output paths for the clock and data signals, skew between the clock and data signals is minimized.
In one aspect, the present invention provides a circuit comprising a plurality of channel circuits in which each channel includes a shift register circuit, a flip-flop circuit, and a multiplexer circuit. The shift register circuit receives a plurality of input bit signals in parallel and shifts out a serial output signal in response. The shift register circuit is triggered by an input clock signal. The flip-flop circuit, which may be a delay-type flip-flop circuit, receives the register output signal at an input thereof and provides a flip-flop output signal in response. The flip-flop circuit is also triggered by the input clock signal. The multiplexer circuit receives the register output signal and the flip-flop output signal at first and second inputs. The multiplexer circuit is configured, e.g., programmed, to output the signal at one of the multiplexer inputs as a channel output signal. In one embodiment, the input clock-to-output delay of the shift register is substantially the same as the input clock-to-output delay of the flip-flop circuit.
In one embodiment, at least one channel circuit is a frequency-divided clock channel circuit in which the plurality of parallel input bit signals received by the shift register are fixed digital signals. In this case, the register output signal and the flip-flop output signal in that channel are each clock signals having a frequency that is divided down by a factor of at least two with respect to the input clock signal. The frequency may also be divided down by a factor of 3, 4, or any other integer amount. The fixed digital signals may be programmable to facilitate clock frequency selection. In one embodiment, in each frequency-divided clock channel circuit, the shift register is triggered by a first (e.g., rising) edge in the input clock signal and the flip-flop circuit is triggered by a second (e.g. falling) edge in the input clock signal, so that the register output clock signal and the flip-flop output clock signal have a phase difference equivalent in time to one half cycle of the input clock signal.
In another embodiment, at least one channel circuit is a data channel circuit in which the plurality of parallel input bit signals received by the shift register are data signals. In this case the register output signal is a serial data signal, and the multiplexer circuit in each of the data channel circuits is configured to output the serial data signal as the channel output signal.
In another embodiment, each channel circuit also includes a delay circuit for receiving the input clock signal and outputting a delayed version of the input clock signal. In this embodiment, the multiplexer circuit in each channel includes a third input for receiving the delayed version of the input clock signal. Also in this embodiment, the propagation delay of the input clock in the delay circuit is further matched with the input clock-to-output delay of the shift register and the input clock-to-output delay of the flip-flop circuit. The delay circuit may also include a programmable polarity selection input. When the polarity selection input is in a first state the delayed version of the input clock signal has substantially the same polarity as the input clock signal, while when the polarity selection input is in a second state the delayed version of the input clock signal has a substantially opposite polarity to the input clock signal. The delay circuit may comprise a delay multiplexer circuit having a first input for receiving the polarity selection input, a second input for receiving a complement of the polarity selection input, and a selection input for receiving the input clock signal.
In another aspect, the present invention provides a circuit for providing a clock signal comprising a shift register circuit, a flip-flop circuit, and a multiplexer circuit. The shift register circuit receives a plurality of fixed clock frequency select bit signals in parallel and shifts out an output clock signal in response. The shift register circuit is triggered by an input clock signal, and the register output clock signal has a frequency that is divided down by a factor of at least two with respect to the input clock signal. The flip-flop circuit receives the register output clock signal at an input thereof and provides a flip-flop output clock signal in response. The flip-flop circuit is triggered by the input clock signal, and the flip-flop output clock signal has the same frequency as the register output clock signal. The multiplexer circuit receives the register output clock signal and the flip-flop output clock signal at first and second multiplexer inputs. The multiplexer circuit is configurable to output the signal at one of the multiplexer inputs as a clock output signal. Optionally, the circuit may further include a delay circuit for receiving the input clock signal and outputting a delayed version of the input clock signal. If so, the multiplexer circuit has a third input for receiving the delayed version of the input clock signal.
The circuit may further include a circuit for providing a data signal which includes: a second shift register circuit for receiving a plurality of data bit signals in parallel and shifting out a serial data signal in response; and a second multiplexer circuit for receiving the serial data signal at an input thereof. The second shift register circuit is also triggered by the input clock signal, and the second multiplexer circuit is configured to output the serial data signal. In one embodiment, the input clock-to-output delay of the second shift register is substantially the same as the input clock-to-output delay of the first shift register and as the input clock-to-output delay of the flip-flop circuit.